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EDI88257C
HI-RELIABILITY PRODUCT
256Kx8 Monolithic SRAM
FEATURES
s 256Kx8 CMOS Static s Random Access Memory * Access Times of 70, 85, 100ns * Data Retention Function (LP Versions) * TTL Compatible Inputs and Outputs * Fully Static, No Clocks s JEDEC Approved Pinout * 32 pin Ceramic DIP, 0.6 mils wide (Package 9) s Single +5V (10%) Supply Operation The EDI88257C is a 2 Megabit 256Kx8 bit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the JEDEC standard for the two megabit device, and is a pin replacement for the 256Kx8 module, EDI88257C. The device is upgradeable to the 512Kx8 SRAM, the EDI88512C. Pin 1 becomes the higher order address. A Low Power version, EDI88257LP, offers a data retention function for battery back-up opperation. Military product is available compliant to Appendix A of MIL-PRF-38535.
FIG. 1
PIN CONFIGURATION PIN DESCRIPTION
32 DIP
A0-17 W
32 VCC 31 A15 30 A17 29 W 28 A13 27 A8 26 A9 25 A11 24 G 23 A10 22 E 21 DQ7 20 DQ6 19 DQ5 18 DQ4 17 DQ3
AO-17
TOP VIEW
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AO DQO DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Address Inputs Write Enable Chip Enable Output Enable Data Inputs/Outputs Power (+5V 10%) Ground Not Connected
E G DQ0-7 VCC VSS
BLOCK DIAGRAM
Memory Array
NC
Address Buffer
Address Decoder
I/O Circuits
DQO-7
W E G
September 1999 Rev. 2
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White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
EDI88257C
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Operating Temperature TA (Ambient) Industrial Military Storage Temperature, Ceramic Power Dissipation Output Current Junction Temperature, TJ -40 to +85 -55 to +125 -65 to +150 1 20 175 C C C W mA C -0.5 to 7.0 Unit V G X H L X E H L L L W X H H L
TRUTH TABLE
Mode Standby Output Deselect Read Write Output High Z High Z Data Out Data In Power Icc2, Icc3 Icc1 Icc1 Icc1
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 -- -- Max 5.5 0 Vcc +0.5 +0.8 Unit V V V V
NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
Parameter Address Lines Data Lines Symbol CI CD/Q Condition VIN = Vcc or Vss, f = 1.0MHz VOUT = Vcc or Vss, f = 1.0MHz Max 30 14 Unit pF pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS (VCC = 5V, TA = +25C)
Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current Output Low Voltage Output High Voltage Symbol ILI ILO ICC1 ICC2 ICC3 VOL VOH VIN = 0V to VCC VI/O = 0V to VCC W, E = VIL, II/O = 0mA, Min Cycle E VIH, VIN VIL, VIN VIH E VCC -0.2V VIN Vcc -0.2V or VIN 0.2V IOL = 2.1mA IOH = -1.0mA C LP (70-100ns) Conditions Min -- -- -- -- -- -- -- 2.4 Typ -- -- 45 3 -- -- -- -- Max 10 10 75 10 5 1 0.4 -- A A mA mA mA mA V V Units
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
480
480
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load
VSS to 3.0V 5ns 1.5V Figure 1
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
Q 255 30pF Q 255 5pF
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EDI88257C
AC CHARACTERISTICS - READ CYCLE (VCC = 5.0V, VSS = 0V, TA = -55C to +125C))
Parameter Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z (1) Symbol JEDEC Alt. tAVAV tAVQV tELQV tELQX tEHQZ tAVQX tGLQV tGLQX tGHQZ tRC tAA tACS tCLZ tCHZ tOH tOE tOLZ tOHZ 5 0 25 10 35 5 0 30 10 25 10 45 5 0 30 70ns Min 70 70 70 10 30 10 50 Max Min 85 85 85 10 30 85ns Max Min 100 100 100 100ns Max Units ns ns ns ns ns ns ns ns ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS - WRITE CYCLE (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Parameter Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) Symbol JEDEC Alt. tAVAV tELWH tELEH tAVWL tAVEL tAVWH tAVEH tWLWH tWLEH tWHAX tEHAX tWHDX tEHDX tWLQZ tDVWH tDVEH tWHQX tWC tCW tCW tAS tAS tAW tAW tWP tWP tWR tWR tDH tDH tWHZ tDW tDW tWLZ 70ns Min 70 60 60 0 0 65 65 50 50 0 0 0 0 0 40 30 5 25 Max Min 85 70 70 0 0 70 70 55 55 0 0 0 0 0 40 35 5 30 85ns Max Min 100 80 80 0 0 80 80 60 60 0 0 0 0 0 40 40 5 30 100ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. This parameter is guaranteed by design but not tested.
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EDI88257C
FIG. 2
TIMING WAVEFORM - READ CYCLE
A
tAVAV tAVQV
tAVAV
A
ADDRESS 1 ADDRESS 2
E
tELQV tELQX
G
tEHQZ
tAVQV
Q
tAVQX
DATA 1 DATA 2
tGLQV tGLQX
Q
tGHQZ
READ CYCLE 1 (W HIGH; G, E LOW)
READ CYCLE 2 (W HIGH)
FIG. 3
WRITE CYCLE - W CONTROLLED
tAVAV
A
tAVWH tELWH
E
tWHAX
tAVWL
W
tWLWH tDVWH tWHDX
D
DATA VALID
tWLQZ
Q
HIGH Z
tWHQX
WRITE CYCLE 1, W CONTROLLED
FIG. 4
WRITE CYCLE - E CONTROLLED
A
tAVAV
WS32K32-XHX
tAVEH tELEH tEHAX tAVEL tWLEH tDVEH tEHDX
E
W
D Q
HIGH Z
DATA VALID
WRITE CYCLE 2, E CONTROLLED
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EDI88257C
DATA RETENTION CHARACTERISTICS (EDI88257LP ONLY) (TA = -55C to +125C)
Characteristic Low Power Version only Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time Operation Recovery Time Sym VDD ICCDR TCDR TR Conditions VDD = 2.0V E VDD -0.2V VIN VDD -0.2V or VIN 0.2V Min 2 - 0 TAVAV Typ - - - - Max - 185 - - Units V A ns ns
FIG. 5
DATA RETENTION - E CONTROLLED
Data Retention Mode
Vcc
4.5V VDD
WS32K32-XHX
4.5V
tCDR
E
E = VDD -0.2V
tR
DATA RETENTION, E CONTROLLED
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White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
EDI88257C
PACKAGE 9:
32 PIN SIDEBRAZED CERAMIC DIP (600mils wide)
1.616 1.584
Pin 1 Indicator 0.175 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500
0.060 0.040
0.620 0.600
0.100 TYP
0.155 0.115
0.600 NOM
ALL DIMENSIONS ARE IN INCHES
ORDERING INFORMATION EDI 8 8 257 C X X X
WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 256Kx8 TECHNOLOGY: C = CMOS Standard Power LP = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened -55C to +125C I = Industrial -40C to +85C C = Commercial 0C to +70C
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